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Preliminary Technical Data
FEATURES
<0.5 pC charge injection over full signal range 2.5 pF off capacitance Low leakage; 0.6 nA maximum @ 85C 120 on resistance Fully specified at +12 V, 15 V No VL supply required 3 V logic-compatible inputs Rail-to-rail operation 8-lead SOT-23 package
Low Capacitance, Low Charge Injection, 15 V/12 V iCMOSTM SPDT in SOT-23 ADG1219
FUNCTIONAL BLOCK DIAGRAM
ADG1219
SA SB DECODER D
IN
EN
SWITCHES SHOWN FOR A LOGIC "0" INPUT
Figure 1.
APPLICATIONS
Automatic test equipment Data acquisition systems Battery-powered systems Sample-and-hold systems Audio/video signal routing Communication systems
GENERAL DESCRIPTION
The ADG1219 is a monolithic iCMOS device containing an SPDT switch. An EN input is used to enable or disable the device. When disabled, all channels are switched off. When on, each channel conducts equally well in both directions and has an input signal range that extends to the supplies. Each switch exhibits break-before-make switching action. The iCMOS (industrial CMOS) modular manufacturing process combines high voltage CMOS (complementary metaloxide semiconductor) and bipolar technologies. It enables the development of a wide range of high performance analog ICs capable of 33 V operation in a footprint that no other generation of high voltage parts has been able to achieve. Unlike analog ICs using conventional CMOS processes, iCMOS components can tolerate high supply voltages while providing increased performance, dramatically lower power consumption, and reduced package size. The ultralow capacitance and exceptionally low charge injection of these multiplexers make them ideal solutions for data acquisition and sample-and-hold applications, where low glitch and fast settling are required. Figure 2 shows that there is minimum charge injection over the entire signal range of the device. iCMOS construction also ensures ultralow power dissipation, making the parts ideally suited for portable and battery-powered instruments.
0.5 0.4 0.3
CHARGE INJECTION (pC)
TA = 25C VDD = +15V VSS = -15V
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -15 -10
06574-041
VDD = 12V VSS = 0V
VDD = +5V VSS = -5V -5 0 5 10 15
INPUT VOLTAGE (V)
Figure 2. Charge Injection vs. Input Voltage
Rev. PrB
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
06575-001
ADG1219 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Dual Supply ................................................................................... 3 Single Supply ................................................................................. 4
Preliminary Technical Data
Absolute Maximum Ratings ............................................................6 ESD Caution...................................................................................6 Pin Configuration and Function Descriptions..............................7 Terminology .................................................................................... 14 Typical Performance Characteristics ..............................................8 Test Circuits..................................................................................... 12 Outline Dimensions ....................................................................... 14 Ordering Guide .......................................................................... 15
REVISION HISTORY
7/07--Revision 0: Initial Version
Rev. PrB | Page 2 of 17
Preliminary Technical Data SPECIFICATIONS
DUAL SUPPLY
VDD = 15 V 10%, VSS = -15 V 10%, GND = 0 V, unless otherwise noted. Table 1.
Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk Total Harmonic Distortion + Noise -3 dB Bandwidth CS (Off) CD (Off) CD, CS (On) 25C B Version1 -40C to +85C -40C to +125C VDD to VSS 120 190 3.5 6 20 60 0.01 0.1 0.01 0.1 0.02 0.2 0.6 0.6 0.6 1 1 1 2.0 0.8 0.005 0.1 2 140 170 85 105 105 125 40 0.1 77 80 0.15 520 2.5 3.3 4.3 5.1 7.5 10 230 260 Unit V typ max typ max typ max nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ % typ MHz typ pF typ pF max pF typ pF max pF typ pF max
ADG1219
Test Conditions/Comments
VS = 10 V, IS = -1 mA; see Figure 23 VDD = +13.5 V, VSS = -13.5 V VS = 10 V, IS = -1 mA
10 72
12 79
VS = -5 V, 0 V, +5 V; IS = -1 mA VDD = +16.5 V, VSS = -16.5 V VS = 10 V, VS = 10 V; see Figure 24 VS = 10 V, VS = 10 V; see Figure 24 VS = VD = 10 V; see Figure 25
VIN = VINL or VINH
200 130 150
230 140 170 10
RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS = 10 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 10 V; Figure 27 VS = 0 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 10 k, 5 V rms, f = 20 Hz to 20 kHz RL = 50 , CL = 5 pF; see Figure 31 f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V f = 1 MHz; VS = 0 V
Rev. PrB | Page 3 of 17
ADG1219
Parameters POWER REQUIREMENTS IDD IDD ISS VDD/VSS
1 2
Preliminary Technical Data
25C 0.001 1.0 140 170 0.001 1.0 5/16.5 B Version1 -40C to +85C -40C to +125C Unit A typ A max A typ A max A typ A max V min/max Test Conditions/Comments VDD = +16.5 V, VSS = -16.5 V Digital inputs = 0 V or VDD Digital inputs = 5 V Digital inputs = 0 V, 5 V or VDD |VDD | = |VSS|
Temperature range for B version is -40C to +125C. Guaranteed by design; not subject to production test.
SINGLE SUPPLY
VDD = 12 V 10%, VSS = 0 V, GND = 0 V, unless otherwise noted. Table 2.
Parameters ANALOG SWITCH Analog Signal Range On Resistance (RON) On Resistance Match Between Channels (RON) On Resistance Flatness (RFLAT(ON)) LEAKAGE CURRENTS Source Off Leakage, IS (Off) Drain Off Leakage, ID (Off) Channel On Leakage, ID, IS (On) DIGITAL INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IINL or IINH Digital Input Capacitance, CIN DYNAMIC CHARACTERISTICS2 Transition Time, tTRANSITION tON (EN) tOFF (EN) Break-Before-Make Time Delay, tBBM Charge Injection Off Isolation Channel-to-Channel Crosstalk -3 dB Bandwidth 25C B Version1 -40C to +85C -40C to +125C 0 V to VDD 300 475 4.5 16 60 0.01 0.1 0.01 0.1 0.02 0.2 567 625 Unit V typ max typ max typ nA typ nA max nA typ nA max nA typ nA max V min V max A typ A max pF typ ns typ ns max ns typ ns max ns typ ns max ns typ ns min pC typ dB typ dB typ MHz typ
Rev. PrB | Page 4 of 17
Test Conditions/Comments
VS = 0 V to 10 V, IS = -1 mA; see Figure 23 VDD = 10.8 V, VSS = 0 V VS = 0 V to 10 V, IS = -1 mA
26
27
VS = 3 V, 6 V, 9 V, IS = -1 mA VDD = 13.2 V VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = 1 V/10 V, VD = 10 V/1 V; see Figure 24 VS = VD = 1 V or 10 V, see Figure 25
0.6 0.6 0.6
1 1 1 2.0 0.8
0.001 0.1 3 195 250 120 150 145 185 70 -0.8 80 80 400
VIN = VINL or VINH
300 190 220
340 210 235 10
RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS = 8 V; see Figure 26 RL = 300 , CL = 35 pF VS1 = VS2 = 8 V; see Figure 27 VS = 6 V, RS = 0 , CL = 1 nF; see Figure 28 RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 29; RL = 50 , CL = 5 pF, f = 1 MHz; see Figure 30 RL = 50 , CL = 5 pF; see Figure 31
Preliminary Technical Data
Parameters CS (Off) CD (Off) CD, CS (On) POWER REQUIREMENTS IDD IDD VDD
1 2
ADG1219
B Version1 -40C to +85C -40C to +125C Unit pF typ pF max pF typ pF max pF typ pF max A typ A max A typ A max V min/max Test Conditions/Comments f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V f = 1 MHz; VS = 6 V VDD = 13.2 V Digital inputs = 0 V or VDD Digital inputs = 5 V VSS = 0 V, GND = 0 V
25C 2.9 3.7 5 5.8 8.5 11 0.001
1.0 140 170 5/16.5
Temperature range for B version is -40C to +125C. Guaranteed by design; not subject to production test.
Rev. PrB | Page 5 of 17
ADG1219 ABSOLUTE MAXIMUM RATINGS
TA = 25C, unless otherwise noted. Table 3.
Parameter VDD to VSS VDD to GND VSS to GND Analog Inputs1 Digital Inputs1 Peak Current, S or D Continuous Current per Channel, S or D Operating Temperature Range Industrial (B Version) Storage Temperature Range Junction Temperature 8-Lead SOT-23, JA Thermal Impedance Reflow Soldering Peak Temperature, Pb Free
1
Preliminary Technical Data
Rating 35 V -0.3 V to +25 V +0.3 V to -25 V VSS - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first GND - 0.3 V to VDD + 0.3 V or 30 mA, whichever occurs first 100 mA (pulsed at 1 ms, 10% duty cycle maximum) 30 mA
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ESD CAUTION
-40C to +125C -65C to +150C 150C 211.5C/W 260C
Overvoltages at IN, S, or D are clamped by internal diodes. Current should be limited to the maximum ratings given.
Rev. PrB | Page 6 of 17
Preliminary Technical Data PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
EN 1 VDD 2 GND 3
8
ADG1219
IN
NC = NO CONNECT
Figure 3. SOT-23 Pin Configuration
Table 4. Pin Function Descriptions
Pin No.
1
2 3 4 5 6 7 8
Mnemonic EN VDD GND VSS SB D SA IN
Description Active High Digital Input. When this pin is low, the device is disabled and all switches are turned off. When this pin is high, the IN logic input determines which switch is turned on. Most Positive Power Supply Potential. Ground (0 V) Reference. Most Negative Power Supply Potential. Source Terminal. Can be an input or output. Drain Terminal. Can be an input or output. Source Terminal. Can be an input or output. Logic Control Input.
Table 5. Truth Table
EN 0 1 1 IN X 0 1 Switch A Off On Off Switch B Off Off On
Rev. PrB | Page 7 of 17
06575-003
SA TOP VIEW 6D (Not to Scale) VSS 4 5 SB
7
ADG1219
ADG1219 TYPICAL PERFORMANCE CHARACTERISTICS
200 180 160 TA = 25C VDD = 13.5V VSS = -13.5V VDD = 15V VSS = -15V 200 250
Preliminary Technical Data
VDD = 15V VSS = -15V
ON RESISTANCE ()
ON RESISTANCE ()
140 120 100 80 60 40
06575-004
TA = +125C 150 TA = +85C TA = +25C 100 TA = -40C 50
06575-007
VDD = 16.5V VSS = -16.5V
20 0 -18 -15 -12 -9 -6 -3 0 3 6 9 SOURCE OR DRAIN VOLTAGE (V) 12 15 18
0 -15
-10
-5 0 5 TEMPERATURE (C)
10
15
Figure 4. On Resistance as a Function of VD (VS) for Dual Supply
Figure 7. On Resistance as a Function of VD (VS) for Different Temperatures, Dual Supply
600 VDD = 12V VSS = 0V
600 TA = 25C 500 VDD = 4.5V VSS = -4.5V
TA = +125C 500
ON RESISTANCE ()
ON RESISTANCE ()
VDD = 5V VSS = -5V 400
TA = +85C 400 TA = +25C 300 TA = -40C
300
VDD = 5.5V VSS = -5.5V
200
200
100
06575-005
100
06575-008
0 -6
-4
-2 0 2 SOURCE OR DRAIN VOLTAGE (V)
4
6
0
0
2
4 6 8 TEMPERATURE (C)
10
12
Figure 5. On Resistance as a Function of VD (VS) for Dual Supply
Figure 8. On Resistance as a Function of VD (VS) for Different Temperatures, Single Supply
200
450 TA = 25C 400 350 VDD = 10.8V VSS = 0V VDD = 12V VSS = 0V
100 0
VDD = +15V VSS = -15V VBIAS = +10V/-10V
ON RESISTANCE ()
LEAKAGE (pA)
300 250 200 150 100
06575-006
-100 -200 IS(OFF)+- -300 -400 -500 ID(OFF)+- IS(OFF)-+ ID(OFF)-+ ID,S(ON)- - 0 20 40 60 80 100 120
06575-030
VDD = 13.2V VSS = 0V
50 0 0 2 4 6 8 10 SOURCE OR DRAIN VOLTAGE (V) 12 14
ID,S(ON)++
TEMPERATURE (C)
Figure 6. On Resistance as a Function of VD (VS) for Single Supply
Figure 9. Leakage Currents as a Function of Temperature, 15 V Dual Supply
Rev. PrB | Page 8 of 17
Preliminary Technical Data
350 IS(OFF)+- 300 250 200 150 100 50 0
06575-031
ADG1219
0.5 0.4 0.3 TA = 25C VDD = +15V VSS = -15V
ID(OFF)+- IS(OFF)-+
CHARGE INJECTION (pC)
ID(OFF)-+ ID,S(ON)++ ID,S(ON)- - VDD = 12V VSS = 0V VBIAS = 1V/10V
0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 -15 -10
06574-041
LEAKAGE (pA)
VDD = 12V VSS = 0V
-50 -100
VDD = +5V VSS = -5V -5 0 5 10 15
0
20
40
60
80
100
120
TEMPERATURE (C)
INPUT VOLTAGE (V)
Figure 10.Leakage Currents as a Function of Temperature, 12 V Single Supply
Figure 13. Charge Injection vs. Input Voltage
100 VDD = 5V VSS = -5V VBIAS = +4.5V/-4.5V
300
50
250
12V SS
LEAKAGE (pA)
0
200
-50 IS(OFF)+- ID(OFF)+- IS(OFF)-+ -150 ID(OFF)-+
06575-032
TIME (ns)
150
15V DS
-100
100
ID,S(ON)- - -200 0 20 40 60 80 100 120
0 -40
-20
0
20
40
60
80
100
120
TEMPERATURE (C)
TEMPERATURE (C)
Figure 11. Leakage Currents as a Function of Temperature, 5 V Dual Supply
0
IDD PER CHANNEL TA = 25C
Figure 14. tTRANSITION Time vs. Temperature
200 180 160
-10 -20
VDD = 15V VSS = -15V TA = 25C
ISOLATION (dB)
140 IDD (A) 120 100 80 60 40 20 0 0 2
VDD = +15V VSS = -15V
-30 -40 -50 -60 -70 -80 -90
VDD = +12V VSS = 0V
06575-009
-100
12 14 16
4
6
8 10 LOGIC, INX (V)
-110 10k
100k
1M
10M
100M
1G
FREQUENCY (Hz)
Figure 12. IDD vs. Logic Level
Figure 15. Off Isolation vs. Frequency
Rev. PrB | Page 9 of 17
06575-022
06575-027
ID,S(ON)++
50
ADG1219
0 -10 -20 -30 -40 -50 -60 -70 -80 -90
06575-026
Preliminary Technical Data
8 7 SOURCE/DRAIN ON 6
VDD = 15V VSS = -15V TA = 25C
CAPACITANCE (pF)
CROSSTALK (dB)
5 DRAIN OFF 4 3 2
06575-023
SOURCE OFF
-100 -110 10k 100k 1M 10M 100M 1G
1 0 -15
VDD = 15V VSS = -15V TA = 25C -10 -5 0 5 10 15
FREQUENCY (Hz)
SOURCE VOLTAGE (V)
Figure 16. Crosstalk vs. Frequency
Figure 19. Capacitance vs. Source Voltage for Dual Supply
0 -2 -4 -6 -8 -10 -12 -14 10k VDD = 15V VSS = -15V TA = 25C
9 8 7 SOURCE/DRAIN ON
INSERTION LOSS (dB)
CAPACITANCE (pF)
6 5 4 3 2 SOURCE OFF DRAIN OFF
06575-021
100k
1M
10M
100M
1G
0
0
2
4
6
8
10
12
FREQUENCY (Hz)
SOURCE VOLTAGE (V)
Figure 17. On Response vs. Frequency
Figure 20. Capacitance vs. Source Voltage for Single Supply
10.00 LOAD = 10k TA = 25C
10 9 8 SOURCE/DRAIN ON
1.00 THD + N (%) VDD = 5V, VSS = -5V, VS = 3.5Vrms
CAPACITANCE (pF)
7 6 5 4 3 2 VDD = 5V VSS = -5V TA = 25C -3 -1 1 3 5 SOURCE OFF DRAIN OFF
VDD = 15V, VSS = -15V, VS = 5Vrms 0.10
06575-010
1 0 -5
0.01 10
100
1k FREQUENCY (Hz)
10k
100k
SOURCE VOLTAGE (V)
Figure 18. THD + N vs. Frequency
Figure 21. Capacitance vs. Source Voltage for Dual Supply
Rev. PrB | Page 10 of 17
06575-025
06575-024
1
VDD = 12V VSS = 0V TA = 25C
Preliminary Technical Data
0 -10 -20 -30 VDD = +15V VSS = -15V Vp-p = 0.63V TA = 25C NO DECOUPLING CAPS ON
ADG1219
PSRR (dB)
-40 -50 -60 -70 -80 -90 -100 100k 1M 10M FREQUENCY (Hz)
06576-025
DECOUPLING CAPS ON
100M
Figure 22. ACPSRR vs Frequency
Rev. PrB | Page 11 of 17
ADG1219 TEST CIRCUITS
V S D IDS
06575-011
Preliminary Technical Data
VS
Figure 23. On Resistance
IS (OFF) A VS ID (OFF) A VD
06575-012
06575-013
S
D
Figure 24. Off Leakage
ID (ON) NC S D A VD
NC = NO CONNECT
Figure 25. On Leakage
0.1F
VDD
VSS
0.1F
VIN
50%
50%
VDD VS SB SA IN VIN GND
VSS D RL 300 CL 35pF VOUT VIN 50% 90% 50% 90%
VOUT
tON
tOFF
Figure 26. Switching Times
0.1F VDD VSS 0.1F VIN
VDD VS SB SA IN VIN GND
VSS D RL 300 CL 35pF VOUT
VOUT
80%
tBBM
tBBM
06575-015
Figure 27. Break-Before-Make Time Delay
0.1F VDD VSS 0.1F VIN (NORMALLY CLOSED SWITCH) NC VOUT CL 1nF VIN (NORMALLY OPEN SWITCH) VOUT VOUT
VDD VS D
VSS SB SA
ON
OFF
IN VIN GND
Figure 28. Charge Injection
Rev. PrB | Page 12 of 17
06575-016
QINJ = CL x VOUT
06575-014
Preliminary Technical Data
VDD VSS
ADG1219
0.1F 0.1F
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50
NETWORK ANALYZER VOUT RL 50
VDD SA
VSS
VDD
VSS
IN
SA
D
SB
50 VS VOUT
VS IN
SB
D
R 50
VIN GND VOUT VS
RL 50
GND
06575-017
OFF ISOLATION = 20 log
CHANNEL-TO-CHANNEL CROSSTALK = 20 log
VOUT VS
Figure 29. Off Isolation
Figure 31. Bandwidth
VDD 0.1F
VSS 0.1F NETWORK ANALYZER NC 50
VDD VSS S IN D VIN
06575-018
VDD 0.1F
VSS 0.1F AUDIO PRECISION RS VS V p-p RL 10k VOUT
06575-020
VDD
VSS
IN
SA
SB
50 VS
D
VIN GND RL 50 VOUT
INSERTION LOSS = 20 log
VOUT WITH SWITCH VOUT WITHOUT SWITCH
GND
Figure 30. Channel-to-Channel Crosstalk
Figure 32. THD + Noise
Rev. PrB | Page 13 of 17
06575-019
ADG1219 TERMINOLOGY
IDD The positive supply current. ISS The negative supply current. VD (VS) The analog voltage on Terminal D and Terminal S. RON The ohmic resistance between D and S. RFLAT(ON) Flatness is defined as the difference between the maximum and minimum value of on resistance as measured over the specified analog signal range. IS (Off) The source leakage current with the switch off. ID (Off) The drain leakage current with the switch off. ID, IS (On) The channel leakage current with the switch on. VINL The maximum input voltage for Logic 0. VINH The minimum input voltage for Logic 1. IINL (IINH) The input current of the digital input. CS (Off) The off switch source capacitance, measured with reference to ground. CD (Off) The off switch drain capacitance, measured with reference to ground. CD, CS (On) The on switch capacitance, measured with reference to ground. CIN The digital input capacitance.
Preliminary Technical Data
tON (EN) Delay time between the 50% and 90% points of the digital input and switch on condition. tOFF (EN) Delay time between the 50% and 90% points of the digital input and switch off condition. tTRANSITION Delay time between the 50% and 90% points of the digital inputs and the switch on condition when switching from one address state to another. TBBM Off time measured between the 80% point of both switches when switching from one address state to another. Charge Injection A measure of the glitch impulse transferred from the digital input to the analog output during switching. Off Isolation A measure of unwanted signal coupling through an off switch. Crosstalk A measure of unwanted signal that is coupled through from one channel to another as a result of parasitic capacitance. Bandwidth The frequency at which the output is attenuated by 3 dB. On Response The frequency response of the on switch. Insertion Loss The loss due to the on resistance of the switch. THD + N The ratio of the harmonic amplitude plus noise of the signal to the fundamental. ACPSRR (AC Power Supply Rejection Ratio) Measures the ability of a part to avoid coupling noise and spurious signals that appear on the supply voltage pin to the output of the switch. The dc voltage on the device is modulated by a sine wave of 0.62 V p-p. The ratio of the amplitude of signal on the output to the amplitude of the modulation is the ACPSRR.
Rev. PrB | Page 14 of 17
Preliminary Technical Data OUTLINE DIMENSIONS
2.90 BSC
ADG1219
8
7
6
5
1.60 BSC
1 2 3 4
2.80 BSC
PIN 1 INDICATOR 0.65 BSC 1.30 1.15 0.90 1.95 BSC
1.45 MAX 0.38 0.22
0.22 0.08 8 4 0
0.15 MAX
SEATING PLANE
0.60 0.45 0.30
COMPLIANT TO JEDEC STANDARDS MO-178-BA
Figure 33. 8-Lead Lead Small Outline Transistor Package [SOT-23] (RJ-8) Dimensions shown in millimeters
ORDERING GUIDE
Model ADG1219BRJZ-R21 ADG1219BRJZ-REEL71
1
Temperature Range -40C to +125C -40C to +125C
Package Description 8-Lead Lead Small Outline Transistor Package [SOT-23] 8-Lead Lead Small Outline Transistor Package [SOT-23]
Package Option RJ-8 RJ-8
Branding S24 S24
Z = RoHS Compliant Part.
Rev. PrB | Page 15 of 17
ADG1219 NOTES
Preliminary Technical Data
Rev. PrB | Page 16 of 17
Preliminary Technical Data NOTES
ADG1219
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. PR06575-0-3/08(PrB)
Rev. PrB | Page 17 of 17

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